Today's integrated circuits include a vast number of devices. Smaller devices and shrinking ground rules are the key to enhance performance and to improve reliability. As FET (Field-Effect-Transistor) devices are being scaled down, the technology becomes more complex, and changes in device structures and new fabrication methods are needed to maintain the expected performance enhancement from one generation of devices to the next. The mainstay material of microelectronics is silicon (Si), or more broadly, Si based materials. One such Si based material of importance for microelectronics is the silicon-germanium (SiGe) alloy.
There is great difficulty in maintaining performance improvements in devices of deeply submicron generations. Several avenues are being explored for keeping device performance improvements on track. With shortening gate lengths, the so called short channel effects (SCE), most notably the “drain induced barrier lowering” (DIBL) pose severe roadblocks to miniaturization. These effects can be mitigated by introducing basic structural changes in the devices, such as, for instance, using multiple gates.
A proposed way out of this problem is the use of double gated devices. Such a device is not simply a planar structure conducting on one surface, but conducting on two sides of the device body. The reasons that a double gate device can be downscaled further than a regular planar device are relatively complex, but they have been already given in the technical literature, for instance in: “Device Design Considerations for Double-Gate, Ground-Plane, and Single-Gated Ultra-Thin SOI MOSFET's at the 25 nm Channel Length Generation,” by H.-S. P. Wong, et al, 1998 IEDM Tech Dig., pp. 407-10.
A variation of the double gated device is the so called FinFET, or Tri-Gate, device. These devices are non-planar, or three dimensional, structures hosted by a Fin structure. In FinFETs, the body of the transistor is formed in an island rising out of a planar background, typically having both vertical and horizontal surfaces. The gate of the FinFET is engaging the top surface, as well as, the vertically oriented body on both faces, or sides, resulting in three connected planes being used for transistor channel formation. FinFETs/Tri-Gates have several advantages, such as better SCE, better down-scaling potential, and thus, are promising extensions of the mainline semiconductor technology.
A problem with FinFET devices arises precisely from the fact that the channel is formed on multiple connected planes. Where the plains of the FinFET body meet they form an angle, typically of 90°. This gives rise to the well known corner effect device problem. In the corner the electric field pattern during device operation is different than in the planar region of the device. This results in undesirable device effects, most notably in a lowered threshold voltage for the corner region. The more acute the angle at which the top plane and side planes meet, the more pronounced the corner effect is. For the sake of good device performance it would be desirable to eliminate as much as possible sharp corners in FinFET devices by rounding the intersections between the connected planes. One known approach to rounding corners is to expose the Fin structure silicon islands to a H2-anneal. However, the control of this process is quite cumbersome, leading to poor reproducibility during manufacturing.
In general, FinFET devices and their manufacturing is well suited to semiconductor-on-insulator (SOI), usually silicon-on-insulator, technology. SOI devices typically are fabricated in a thin semiconductor layer disposed over an insulator layer. Most commonly, the insulator layer is a so called buried oxide layer on a silicon (Si) substrate.